1. Field
Embodiments of the invention relate to the field of computer systems and more specifically, but not exclusively, to transaction layer link down handling for Peripheral Component Interconnect (PCI) Express.
2. Background Information
Input/output (I/O) devices of a computer system often communicate with the system's central processing unit (CPU) and system memory via a chipset. The chipset may include a memory controller and an input/output controller. Devices of the computer system may be connected using various buses, such as a Peripheral Component Interconnect (PCI) bus.
A new generation of PCI bus, called PCI Express, has been promulgated by the PCI Special Interest Group. PCI Express uses high-speed serial signaling and allows for point-to-point communication between devices. Communications along a PCI Express connection are made using packets. Interrupts are also made using packets by using the Message Signal Interrupt scheme.
A surprise removal of a device from a PCI Express connection causes a link down condition and may result in a computer system crash. Current schemes may require software intervention or resetting of the system to clean up outstanding communications interrupted by the removal of the device. Today's systems fail to adequately handle link down situations of the PCI Express transaction layer.